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Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures
(2009)
This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SOI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of ...
In-depth low frequency noise evaluation of substrate rotation and strain engineering in N-type triple gate SOI Finfets
(2015)
© 2015 Elsevier B.V. All rights reserved.This work presents an experimental analysis of the low-frequency noise and the effective trap density of conventional, strained, rotated and strained-rotated SOI n-type FinFETs, ...
Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors
(2016)
© 2015 IEEE.This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which ...
Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs
(2018)
© 2018 Elsevier LtdThis work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate ...
Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures
(2017)
© 2017 IOP Publishing Ltd.This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and ...
Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications
(2006)
We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a ...
Junctionless multiple-gate transistors for analog applications
(2011)
This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. ...
A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors
(2013)
This work proposes a physically-based definition for the threshold voltage, VTH, of junctionless nanowire transistors and a methodology to extract it. The VTH is defined as the point of equal magnitude for the drift and ...
Evaluation of graded-channel SOI MOSFET operation at high temperatures
(2006)
This paper presents a comparative analysis between graded-channel (GC) and conventional fully depleted SOI MOSFETs devices operating at high temperatures (up to 300 °C). The electrical characteristics such as threshold ...
Charge-based compact analytical model for triple-gate junctionless nanowire transistors
(2016)
© 2016 Elsevier Ltd.A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin height effects, a new 3-D ...