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In-depth low frequency noise evaluation of substrate rotation and strain engineering in N-type triple gate SOI Finfets

Doria R.T.; De Souza M.A.S.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A. (2015)

© 2015 Elsevier B.V. All rights reserved.This work presents an experimental analysis of the low-frequency noise and the effective trap density of conventional, strained, rotated and strained-rotated SOI n-type FinFETs, ...

Analysis of temperature-induced saturation threshold voltage degradation in deep-submicrometer ultrathin SOI MOSFETs

Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C. (2005)

This paper presents a systematic study of the temperature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed ...

Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior

de Souza M.; Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C. (2007)

This work presents the impact of low temperature operation on the characteristics of uniaxially strained fully-depleted SOI nMOSFETs. Devices with channel lengths down to 160 nm were explored in the range 100-380 K. The ...

Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs

Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C. (2007)

This work studies the impact of uniaxial, biaxial and combined uniaxial-biaxial strain on the linearity of nMOSFETs from a 65 nm fully depleted (FD) SOI technology. The total harmonic distortion (THD) and third-order ...

Cryogenic operation of FinFETs aiming at analog applications

Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C. (2009)

FinFETs are recognized as promising candidates for the CMOS nanometer era. In this paper the most recent results for cryogenic operation of FinFETs will be demonstrated with special emphasis on analog applications. Threshold ...

Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs

Pavanello M.A.; Souza M.D.; Martino J.A.; Simoen E.; Claeys C. (2012)

This work presents the analog performance of n-type triple-gate MuGFETs with high-k dielectrics and TiN gate material fabricated in 45° rotated SOI substrates comparing their performance with standard MuGFETs fabricated ...

The low-frequency noise behaviour of graded-channel SOI nMOSFETs

Simoen E.; Claeys C.; Chung T.M.; Flandre D.; Pavanello M.A.; Martino J.A.; Raskin J.-P. (2007)

It is shown that the low-frequency noise in graded-channel (GC) SOI nMOSFETs is generally of the flicker or 1/f noise type. The corresponding input-referred noise spectral density is markedly higher than for the conventional ...

Impact of halo implantation on 0.13 μm floating body partially depleted SOI n-MOSFETs in low temperature operation

Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C. (2005)

This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation. Parameters such as the drain ...

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Pavanello M.A.; Martino J.A.; Simoen E.; Rooyackers R.; Collaert N.; Claeys C. (2008)

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is ...

Evaluation of triple-gate FinFETs with SiO2-HfO2-TiN gate stack under analog operation

Pavanello M.A.; Martino J.A.; Simoen E.; Rooyackers R.; Collaert N.; Claeys C. (2007)

This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation ...