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In-depth low frequency noise evaluation of substrate rotation and strain engineering in N-type triple gate SOI Finfets

Doria R.T.; De Souza M.A.S.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A. (2015)

© 2015 Elsevier B.V. All rights reserved.This work presents an experimental analysis of the low-frequency noise and the effective trap density of conventional, strained, rotated and strained-rotated SOI n-type FinFETs, ...

Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors

Trevisoli R.; Doria R.T.; De Souza M.; Barraud S.; Vinet M.; Pavanello M.A. (2016)

© 2015 IEEE.This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which ...

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A. (2018)

© 2018 Elsevier LtdThis work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate ...

Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures

Doria R.T.; Flandre D.; Trevisoli R.; De Souza M.; Pavanello M.A. (2017)

© 2017 IOP Publishing Ltd.This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and ...

Junctionless multiple-gate transistors for analog applications

Doria R.T.; Pavanello M.A.; Trevisoli R.D.; De Souza M.; Lee C.-W.; Ferain I.; Akhavan N.D.; Yan R.; Razavi P.; Yu R.; Kranti A.; Colinge J.-P. (2011)

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. ...

A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors

Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A. (2013)

This work proposes a physically-based definition for the threshold voltage, VTH, of junctionless nanowire transistors and a methodology to extract it. The VTH is defined as the point of equal magnitude for the drift and ...

Charge-based compact analytical model for triple-gate junctionless nanowire transistors

Avila-Herrera F.; Paz B.C.; Cerdeira A.; Estrada M.; Pavanello M.A. (2016)

© 2016 Elsevier Ltd.A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin height effects, a new 3-D ...

Threshold voltage in junctionless nanowire transistors

Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A. (2011)

This work presents a physically based analytical model for the threshold voltage in junctionless nanowire transistors (JNTs). The model is based on the solution of the two-dimensional Poisson equation and includes the ...

Junctionless nanowire transistors operation at temperatures down to 4.2 K

Trevisoli R.; De Souza M.; Doria R.T.; Kilchtyska V.; Flandre D.; Pavanello M.A. (2016)

© 2016 IOP Publishing Ltd.The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the ...

High temperature effects on harmonic distortion in submicron SOI graded-channel MOSFETs

Emam M.; Pavanello M.A.; Danneville F.; Vanhoenacker-Janvier D.; Raskin J.-P. (2011)

The effect of elevated temperature on the harmonic distortion in Graded-Channel MOSFETs is presented in this work. The Graded-Channel devices show interesting advantages in terms of nonlinear behavior compared to classical ...