Description
© 2015 IEEE.This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which includes shortchannel effects, and accounts for the dependences on the device dimensions, doping concentration, and quantum effects. It is validated with 3-D Technology Computer-Aided Design (TCAD) simulations for several device characteristics and biases as well as with the experimental results.
