| dc.contributor.author | Trevisoli R. | |
| dc.contributor.author | Doria R.T. | |
| dc.contributor.author | De Souza M. | |
| dc.contributor.author | Barraud S. | |
| dc.contributor.author | Vinet M. | |
| dc.contributor.author | Pavanello M.A. | |
| dc.date.accessioned | 2019-08-19T23:45:11Z | |
| dc.date.available | 2019-08-19T23:45:11Z | |
| dc.date.issued | 2016 | |
| dc.identifier.citation | TREVISOLI, RENAN; Doria, Rodrigo Trevisoli; DE SOUZA, Michelly; BARRAUD, SYLVAIN; VINET, MAUD; Pavanello, Marcelo Antonio. Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 63, n. 2, p. 856-863, 2016. | |
| dc.identifier.issn | 0018-9383 | |
| dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/1112 | |
| dc.description.abstract | © 2015 IEEE.This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which includes shortchannel effects, and accounts for the dependences on the device dimensions, doping concentration, and quantum effects. It is validated with 3-D Technology Computer-Aided Design (TCAD) simulations for several device characteristics and biases as well as with the experimental results. | |
| dc.relation.ispartof | IEEE Transactions on Electron Devices | |
| dc.rights | Acesso Restrito | |
| dc.title | Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors | |
| dc.type | Artigo | |
