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Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors

Trevisoli R.; Doria R.T.; De Souza M.; Barraud S.; Vinet M.; Pavanello M.A. (2016)

© 2015 IEEE.This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which ...

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A. (2018)

© 2018 Elsevier LtdThis work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate ...

Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A. (2019)

© 2019 Elsevier LtdThis work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow ...

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K

Paz B.C.; Doria R.T.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A. (2017)

© 2017 Elsevier LtdThe linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed ...

Drain current model for short-channel triple gate junctionless nanowire transistors

Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Faynot O.; Avila-Herrera F.; Cerdeira A.; Pavanello M.A. (2016)

© 2016 Elsevier LtdThis work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration ...

Junctionless nanowire transistors parameters extraction based on drain current measurements

Trevisoli R.; Doria R.T.; de Souza M.; Barraud S.; Pavanello M.A. (2019)

© 2019 Elsevier LtdThe aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As ...

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Trevisoli R.; Doria R.T.; Barraud S.; Pavanello M.A. (2019)

© 2019 Elsevier B.V.The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain ...

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Doria R.T.; Trevisoli R.; de Souza M.; Barraud S.; Vinet M.; Faynot O.; Pavanello M.A. (2017)

© 2017 Elsevier B.V.This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire transistors (JNTs) on the substrate bias. ...

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K

Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A. (2017)

© 2016 Elsevier LtdThis work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires ...