Search

Now showing items 31-40 of 58

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K

Paz B.C.; Doria R.T.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A. (2017)

© 2017 Elsevier LtdThe linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed ...

Cryogenic operation of FinFETs aiming at analog applications

Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C. (2009)

FinFETs are recognized as promising candidates for the CMOS nanometer era. In this paper the most recent results for cryogenic operation of FinFETs will be demonstrated with special emphasis on analog applications. Threshold ...

Drain current model for short-channel triple gate junctionless nanowire transistors

Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Faynot O.; Avila-Herrera F.; Cerdeira A.; Pavanello M.A. (2016)

© 2016 Elsevier LtdThis work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration ...

Junctionless nanowire transistors parameters extraction based on drain current measurements

Trevisoli R.; Doria R.T.; de Souza M.; Barraud S.; Pavanello M.A. (2019)

© 2019 Elsevier LtdThe aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As ...

Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs

Pavanello M.A.; Souza M.D.; Martino J.A.; Simoen E.; Claeys C. (2012)

This work presents the analog performance of n-type triple-gate MuGFETs with high-k dielectrics and TiN gate material fabricated in 45° rotated SOI substrates comparing their performance with standard MuGFETs fabricated ...

Approximate analytical expression for the tersminal voltage in multi-exponential diode models

Ortiz-Conde A.; Garcia-Sanchez F.J.; Teran Barrios A.; Muci J.; De Souza M.; Pavanello M.A. (2013)

We propose a simple approximate solution for the terminal voltage as an explicit function of the terminal current for diodes which need to be modeled by two or more ideal diodes in parallel. As a result, this solution is ...

The low-frequency noise behaviour of graded-channel SOI nMOSFETs

Simoen E.; Claeys C.; Chung T.M.; Flandre D.; Pavanello M.A.; Martino J.A.; Raskin J.-P. (2007)

It is shown that the low-frequency noise in graded-channel (GC) SOI nMOSFETs is generally of the flicker or 1/f noise type. The corresponding input-referred noise spectral density is markedly higher than for the conventional ...

Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range

Pavanello M.A.; Cerdeira A.; Doria R.T.; Ribeiro T.A.; Avila-Herrera F.; Estrada M. (2019)

© 2019 Elsevier LtdThis paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics ...

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

Doria R.T.; Cerdeira A.; Raskin J.-P.; Flandre D.; Pavanello M.A. (2008)

In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-around (GAA) devices operating in saturation region for analog applications. The study has been performed through device ...

Compact model for short-channel symmetric double-gate junctionless transistors

Avila-Herrera F.; Cerdeira A.; Paz B.C.; Estrada M.; Iniguez B.; Pavanello M.A. (2015)

© 2015 Elsevier Ltd.Abstract In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage ...