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In-depth low frequency noise evaluation of substrate rotation and strain engineering in N-type triple gate SOI Finfets

Doria R.T.; De Souza M.A.S.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A. (2015)

© 2015 Elsevier B.V. All rights reserved.This work presents an experimental analysis of the low-frequency noise and the effective trap density of conventional, strained, rotated and strained-rotated SOI n-type FinFETs, ...

Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications

Pavanello M.A.; Der Agopian P.G.; Martino J.A.; Flandre D. (2006)

We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a ...

Evaluation of graded-channel SOI MOSFET operation at high temperatures

Galeti M.; Pavanello M.A.; Martino J.A. (2006)

This paper presents a comparative analysis between graded-channel (GC) and conventional fully depleted SOI MOSFETs devices operating at high temperatures (up to 300 °C). The electrical characteristics such as threshold ...

Analysis of temperature-induced saturation threshold voltage degradation in deep-submicrometer ultrathin SOI MOSFETs

Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C. (2005)

This paper presents a systematic study of the temperature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed ...

Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor

Cerdeira A.; Aleman M.A.; Pavanello M.A.; Martino J.A.; Vancaillie L.; Flandre D. (2005)

In this paper, we analyze the previously unexpected advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters. The ...

Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

Pavanello M.A.; De Souza M.; Ribeiro T.A.; Martino J.A.; Flandre D. (2016)

© 2016 IOP Publishing Ltd.This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped ...

Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior

de Souza M.; Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C. (2007)

This work presents the impact of low temperature operation on the characteristics of uniaxially strained fully-depleted SOI nMOSFETs. Devices with channel lengths down to 160 nm were explored in the range 100-380 K. The ...

Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs

Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C. (2007)

This work studies the impact of uniaxial, biaxial and combined uniaxial-biaxial strain on the linearity of nMOSFETs from a 65 nm fully depleted (FD) SOI technology. The total harmonic distortion (THD) and third-order ...

Cryogenic operation of FinFETs aiming at analog applications

Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C. (2009)

FinFETs are recognized as promising candidates for the CMOS nanometer era. In this paper the most recent results for cryogenic operation of FinFETs will be demonstrated with special emphasis on analog applications. Threshold ...

Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs

Pavanello M.A.; Souza M.D.; Martino J.A.; Simoen E.; Claeys C. (2012)

This work presents the analog performance of n-type triple-gate MuGFETs with high-k dielectrics and TiN gate material fabricated in 45° rotated SOI substrates comparing their performance with standard MuGFETs fabricated ...