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Charge-based compact analytical model for triple-gate junctionless nanowire transistors

Avila-Herrera F.; Paz B.C.; Cerdeira A.; Estrada M.; Pavanello M.A. (2016)

© 2016 Elsevier Ltd.A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin height effects, a new 3-D ...

Compact core model for Symmetric Double-Gate Junctionless Transistors

Cerdeira A.; Avila F.; Iniguez B.; De Souza M.; Pavanello M.A.; Estrada M. (2014)

A new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including ...

Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors

Cerdeira A.; Estrada M.; Iniguez B.; Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A. (2013)

A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 × 1018 and 1 × 10 19 cm-3, as well as ...

Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor

Cerdeira A.; Aleman M.A.; Pavanello M.A.; Martino J.A.; Vancaillie L.; Flandre D. (2005)

In this paper, we analyze the previously unexpected advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters. The ...

Drain current model for short-channel triple gate junctionless nanowire transistors

Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Faynot O.; Avila-Herrera F.; Cerdeira A.; Pavanello M.A. (2016)

© 2016 Elsevier LtdThis work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration ...

Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range

Pavanello M.A.; Cerdeira A.; Doria R.T.; Ribeiro T.A.; Avila-Herrera F.; Estrada M. (2019)

© 2019 Elsevier LtdThis paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics ...

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

Doria R.T.; Cerdeira A.; Raskin J.-P.; Flandre D.; Pavanello M.A. (2008)

In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-around (GAA) devices operating in saturation region for analog applications. The study has been performed through device ...

Compact model for short-channel symmetric double-gate junctionless transistors

Avila-Herrera F.; Cerdeira A.; Paz B.C.; Estrada M.; Iniguez B.; Pavanello M.A. (2015)

© 2015 Elsevier Ltd.Abstract In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage ...

Double-gate junctionless transistor model including short-channel effects

Paz B.C.; Avila-Herrera F.; Cerdeira A.; Pavanello M.A. (2015)

© 2015 IOP Publishing Ltd.This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), ...