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A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation
(2005)
In this work a continuous analytical model for analog simulation of submicron asymmetrically doped silicon-on-insulator (SOI) nMOSFET using the graded-channel (GC) architecture, valid from weak to strong inversion regimes, ...
Double-gate junctionless transistor model including short-channel effects
(2015)
© 2015 IOP Publishing Ltd.This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), ...
An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices
(2012)
Triple-gate devices are considered a promising solution for sub-20 nm era. Strain engineering has also been recognized as an alternative due to the increase in the carriers mobility it propitiates. The simulation of strained ...
Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS
(2006)
This paper studies the performance of operational transconductance amplifiers (OTAs) fabricated with Graded-Channel (GC) SOI nMOSFETs and designed to provide high open-loop voltage gain or high gain-bandwidth characteristics. ...
Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS
(2011)
This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this ...
Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K
(2017)
© 2016 Elsevier LtdThis work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires ...
Modeling of thin-film lateral SOI PIN diodes with an alternative multi-branch explicit current model
(2012)
We propose the use of an alternative multi-exponential model to describe multiple conduction mechanisms in thin-film SOI PIN diodes with parasitic series resistance over a wide operating temperature range, from 90 to 390 ...
Physical insights on the dynamic response of SOI n-and p-type junctionless nanowire transistors
(2018)
© 2018, Brazilian Microelectronics Society. All rights reserved.— This work evaluates, for the first time, the roles of the intrinsic capacitances and the series resistance on the dynamic response of p-and n-type Junctionless ...