Search
Now showing items 21-30 of 58
Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors
(2013)
A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 × 1018 and 1 × 10 19 cm-3, as well as ...
Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs
(2013)
In this work a comparison between the performance of current mirrors implemented with uniformly doped and graded-channel (GC) transistors operating down to low temperature (150 K) is presented. This analysis has been carried ...
Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor
(2005)
In this paper, we analyze the previously unexpected advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters. The ...
Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature
(2016)
© 2016 IOP Publishing Ltd.This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped ...
Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors
(2014)
This work presents an evaluation of the Low-Frequency Noise (LFN) exhibited by short-channel Junctionless Nanowire Transistors (JNTs). Unlike in previous works in which only the noise of n-type transistors was evaluated, ...
Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior
(2007)
This work presents the impact of low temperature operation on the characteristics of uniaxially strained fully-depleted SOI nMOSFETs. Devices with channel lengths down to 160 nm were explored in the range 100-380 K. The ...
Trap density characterization through low-frequency noise in junctionless transistors
(2013)
This work evaluates, for the first time, the trap density of Junctionless Nanowire Transistors (JNTs) of two technologies produced with different gate dielectrics through the low-frequency noise (LFN) characterization. ...
Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs
(2007)
This work studies the impact of uniaxial, biaxial and combined uniaxial-biaxial strain on the linearity of nMOSFETs from a 65 nm fully depleted (FD) SOI technology. The total harmonic distortion (THD) and third-order ...
Substrate bias influence on the operation of junctionless nanowire transistors
(2014)
The aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental results, accomplished by modeled data. The threshold voltage, ...
Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs
(2019)
© 2019 Elsevier LtdThis work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow ...