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Threshold voltage in junctionless nanowire transistors

Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A. (2011)

This work presents a physically based analytical model for the threshold voltage in junctionless nanowire transistors (JNTs). The model is based on the solution of the two-dimensional Poisson equation and includes the ...

Junctionless nanowire transistors operation at temperatures down to 4.2 K

Trevisoli R.; De Souza M.; Doria R.T.; Kilchtyska V.; Flandre D.; Pavanello M.A. (2016)

© 2016 IOP Publishing Ltd.The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the ...

High temperature effects on harmonic distortion in submicron SOI graded-channel MOSFETs

Emam M.; Pavanello M.A.; Danneville F.; Vanhoenacker-Janvier D.; Raskin J.-P. (2011)

The effect of elevated temperature on the harmonic distortion in Graded-Channel MOSFETs is presented in this work. The Graded-Channel devices show interesting advantages in terms of nonlinear behavior compared to classical ...

Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors

Trevisoli R.; Doria R.T.; De Souza M.; Pavanello M.A. (2015)

© 2015 Elsevier B.V. All rights reserved.Abstract This work proposes a method for extracting the energetic distribution of the interface trap density at the gate dielectric in Junctionless silicon Nanowire Transistors. The ...

Compact core model for Symmetric Double-Gate Junctionless Transistors

Cerdeira A.; Avila F.; Iniguez B.; De Souza M.; Pavanello M.A.; Estrada M. (2014)

A new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including ...

Direct determination of threshold condition in DG-MOSFETs from the g m/ID curve

Cunha A.I.A.; Pavanello M.A.; Trevisoli R.D.; Galup-Montoro C.; Schneider M.C. (2011)

In this work we apply the current-based threshold voltage definition (equality between the drift and diffusion components of drain current) to intrinsic symmetric double-gate MOSFETs. We show that the half maximum point ...

On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

De Souza M.; Flandre D.; Doria R.T.; Trevisoli R.; Pavanello M.A. (2016)

© 2015 Elsevier Ltd. All rights reserved.This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two ...

An explicit multi-exponential model for semiconductor junctions with series and shunt resistances

Lugo-Munoz D.; Muci J.; Ortiz-Conde A.; Garcia-Sanchez F.J.; Souza M.D.; Pavanello M.A. (2011)

An alternative explicit multi-exponential model is proposed to describe multiple, arbitrary ideality factor, conduction mechanisms in semiconductor junctions with parasitic series and shunt resistances. This Lambert function ...

Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer

de Souza M.; Flandre D.; Pavanello M.A. (2008)

In this work the performance of graded-channel (GC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with GC ...

Analysis of temperature-induced saturation threshold voltage degradation in deep-submicrometer ultrathin SOI MOSFETs

Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C. (2005)

This paper presents a systematic study of the temperature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed ...

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