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Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors
(2016)
© 2015 IEEE.This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which ...
Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures
(2017)
© 2017 IOP Publishing Ltd.This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and ...
Junctionless nanowire transistors operation at temperatures down to 4.2 K
(2016)
© 2016 IOP Publishing Ltd.The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the ...
Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors
(2015)
© 2015 Elsevier B.V. All rights reserved.Abstract This work proposes a method for extracting the energetic distribution of the interface trap density at the gate dielectric in Junctionless silicon Nanowire Transistors. The ...
On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration
(2016)
© 2015 Elsevier Ltd. All rights reserved.This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two ...
Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors
(2014)
This work presents an evaluation of the Low-Frequency Noise (LFN) exhibited by short-channel Junctionless Nanowire Transistors (JNTs). Unlike in previous works in which only the noise of n-type transistors was evaluated, ...
Substrate bias influence on the operation of junctionless nanowire transistors
(2014)
The aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental results, accomplished by modeled data. The threshold voltage, ...
Junctionless nanowire transistors parameters extraction based on drain current measurements
(2019)
© 2019 Elsevier LtdThe aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As ...
Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors
(2019)
© 2019 Elsevier B.V.The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain ...
Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization
(2017)
© 2017 Elsevier B.V.This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire transistors (JNTs) on the substrate bias. ...