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Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures
(2009)
This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SOI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of ...
Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures
(2017)
© 2017 IOP Publishing Ltd.This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and ...
Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications
(2006)
We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a ...
Illuminated to dark ratio improvement in lateral SOI PIN photodiodes at high temperatures
(2014)
This work presents a study of the illuminated to dark ratio (IDR) of lateral SOI PIN photodiodes. Measurements performed on fabricated devices show a fivefold improvement of the IDR when the devices are biased in accumulation ...
Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment
(2015)
© 2015 IEEE.The impact of high-temperature effects is experimentally investigated in the octagonal layout style for planar silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs), named ...
Influence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs
(2018)
© 2018, Brazilian Microelectronics Society. All rights reserved.This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI ...
Junctionless nanowire transistors operation at temperatures down to 4.2 K
(2016)
© 2016 IOP Publishing Ltd.The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the ...
On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration
(2016)
© 2015 Elsevier Ltd. All rights reserved.This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two ...
Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer
(2008)
In this work the performance of graded-channel (GC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with GC ...
Diamond layout style impact on SOI MOSFET in high temperature environment
(2015)
© 2015 Elsevier Ltd.This work performs an experimental comparative study between the Diamond (hexagonal gate geometry) and Standard layouts styles for Metal-Oxide-Semiconductor Field Effect Transistor in high temperatures ...