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Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures

Doria R.T.; Flandre D.; Trevisoli R.; De Souza M.; Pavanello M.A. (2017)

© 2017 IOP Publishing Ltd.This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and ...

Illuminated to dark ratio improvement in lateral SOI PIN photodiodes at high temperatures

Novo C.; Giacomini R.; Doria R.; Afzalian A.; Flandre D. (2014)

This work presents a study of the illuminated to dark ratio (IDR) of lateral SOI PIN photodiodes. Measurements performed on fabricated devices show a fivefold improvement of the IDR when the devices are biased in accumulation ...

Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment

Gimenez S.P.; Galembeck E.H.S.; Renaux C.; Flandre D. (2015)

© 2015 IEEE.The impact of high-temperature effects is experimentally investigated in the octagonal layout style for planar silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs), named ...

Influence of geometrical parameters on the DC analog behavior of the asymmetric self-cascode FD SOI nMOSFETs

Assalti R.; Flandre D.; de Souza M. (2018)

© 2018, Brazilian Microelectronics Society. All rights reserved.This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI ...

Junctionless nanowire transistors operation at temperatures down to 4.2 K

Trevisoli R.; De Souza M.; Doria R.T.; Kilchtyska V.; Flandre D.; Pavanello M.A. (2016)

© 2016 IOP Publishing Ltd.The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the ...

On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

De Souza M.; Flandre D.; Doria R.T.; Trevisoli R.; Pavanello M.A. (2016)

© 2015 Elsevier Ltd. All rights reserved.This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two ...

Diamond layout style impact on SOI MOSFET in high temperature environment

Gimenez S.P.; Galembeck E.H.S.; Renaux C.; Flandre D. (2015)

© 2015 Elsevier Ltd.This work performs an experimental comparative study between the Diamond (hexagonal gate geometry) and Standard layouts styles for Metal-Oxide-Semiconductor Field Effect Transistor in high temperatures ...

Compact diamond MOSFET model accounting for PAMDLE applicable down 150 nm node

Gimenez S.P.; Davini E.; Peruzzi V.V.; Renaux C.; Flandre D. (2014)

© The Institution of Engineering and Technology 2014.The performance improvements for integrated circuit applications of silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) implemented ...

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs

De Souza M.; Paz B.C.; Flandre D.; Pavanello M.A. (2013)

In this work a comparison between the performance of current mirrors implemented with uniformly doped and graded-channel (GC) transistors operating down to low temperature (150 K) is presented. This analysis has been carried ...

Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

Pavanello M.A.; De Souza M.; Ribeiro T.A.; Martino J.A.; Flandre D. (2016)

© 2016 IOP Publishing Ltd.This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped ...