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A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors

Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A. (2013)

This work proposes a physically-based definition for the threshold voltage, VTH, of junctionless nanowire transistors and a methodology to extract it. The VTH is defined as the point of equal magnitude for the drift and ...

Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors

Doria R.T.; Trevisoli R.; De Souza M.; Pavanello M.A. (2014)

This work presents an evaluation of the Low-Frequency Noise (LFN) exhibited by short-channel Junctionless Nanowire Transistors (JNTs). Unlike in previous works in which only the noise of n-type transistors was evaluated, ...

Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors

Trevisoli R.; Doria R.T.; De Souza M.; Barraud S.; Vinet M.; Pavanello M.A. (2016)

© 2015 IEEE.This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which ...

Trap density characterization through low-frequency noise in junctionless transistors

Doria R.T.; Trevisoli R.D.; De Souza M.; Pavanello M.A. (2013)

This work evaluates, for the first time, the trap density of Junctionless Nanowire Transistors (JNTs) of two technologies produced with different gate dielectrics through the low-frequency noise (LFN) characterization. ...

Threshold voltage in junctionless nanowire transistors

Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A. (2011)

This work presents a physically based analytical model for the threshold voltage in junctionless nanowire transistors (JNTs). The model is based on the solution of the two-dimensional Poisson equation and includes the ...

Physical insights on the dynamic response of SOI n-and p-type junctionless nanowire transistors

Doria R.T.; Trevisoli R.; de Souza M.; Pavanello M.A. (2018)

© 2018, Brazilian Microelectronics Society. All rights reserved.— This work evaluates, for the first time, the roles of the intrinsic capacitances and the series resistance on the dynamic response of p-and n-type Junctionless ...

Junctionless multiple-gate transistors for analog applications

Doria R.T.; Pavanello M.A.; Trevisoli R.D.; De Souza M.; Lee C.-W.; Ferain I.; Akhavan N.D.; Yan R.; Razavi P.; Yu R.; Kranti A.; Colinge J.-P. (2011)

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. ...

In-depth low frequency noise evaluation of substrate rotation and strain engineering in N-type triple gate SOI Finfets

Doria R.T.; De Souza M.A.S.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A. (2015)

© 2015 Elsevier B.V. All rights reserved.This work presents an experimental analysis of the low-frequency noise and the effective trap density of conventional, strained, rotated and strained-rotated SOI n-type FinFETs, ...

On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

De Souza M.; Flandre D.; Doria R.T.; Trevisoli R.; Pavanello M.A. (2016)

© 2015 Elsevier Ltd. All rights reserved.This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two ...

Junctionless nanowire transistors operation at temperatures down to 4.2 K

Trevisoli R.; De Souza M.; Doria R.T.; Kilchtyska V.; Flandre D.; Pavanello M.A. (2016)

© 2016 IOP Publishing Ltd.The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the ...