Centro Universitario FEI: Recent submissions
Now showing items 1481-1500 of 2258
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Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature
(2016)© 2016 IOP Publishing Ltd.This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped ... -
Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior
(2007)This work presents the impact of low temperature operation on the characteristics of uniaxially strained fully-depleted SOI nMOSFETs. Devices with channel lengths down to 160 nm were explored in the range 100-380 K. The ... -
Drain current model for short-channel triple gate junctionless nanowire transistors
(2016)© 2016 Elsevier LtdThis work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration ... -
Analysis of the leakage current in junctionless nanowire transistors
(2013)This letter presents an analysis of the leakage current in Junctionless Nanowire Transistors. The analysis is performed using experimental data together with three-dimensional numerical simulations. The influences of the ... -
Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization
(2017)© 2017 Elsevier B.V.This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire transistors (JNTs) on the substrate bias. ... -
An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices
(2012)Triple-gate devices are considered a promising solution for sub-20 nm era. Strain engineering has also been recognized as an alternative due to the increase in the carriers mobility it propitiates. The simulation of strained ... -
Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K
(2017)© 2016 Elsevier LtdThis work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires ... -
In-depth low frequency noise evaluation of substrate rotation and strain engineering in N-type triple gate SOI Finfets
(2015)© 2015 Elsevier B.V. All rights reserved.This work presents an experimental analysis of the low-frequency noise and the effective trap density of conventional, strained, rotated and strained-rotated SOI n-type FinFETs, ... -
Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors
(2016)© 2015 IEEE.This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which ... -
Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors
(2015)© 2015 Elsevier B.V. All rights reserved.Abstract This work proposes a method for extracting the energetic distribution of the interface trap density at the gate dielectric in Junctionless silicon Nanowire Transistors. The ... -
Compact core model for Symmetric Double-Gate Junctionless Transistors
(2014)A new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including ... -
On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration
(2016)© 2015 Elsevier Ltd. All rights reserved.This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two ... -
Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors
(2013)A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 × 1018 and 1 × 10 19 cm-3, as well as ... -
Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors
(2014)This work presents an evaluation of the Low-Frequency Noise (LFN) exhibited by short-channel Junctionless Nanowire Transistors (JNTs). Unlike in previous works in which only the noise of n-type transistors was evaluated, ... -
Approximate analytical expression for the tersminal voltage in multi-exponential diode models
(2013)We propose a simple approximate solution for the terminal voltage as an explicit function of the terminal current for diodes which need to be modeled by two or more ideal diodes in parallel. As a result, this solution is ... -
Compact model for short-channel symmetric double-gate junctionless transistors
(2015)© 2015 Elsevier Ltd.Abstract In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage ... -
Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors
(2016)© The Institution of Engineering and Technology 2016.In this paper, the performance of asymmetric self-cascode (A-SC) fully depleted silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors ... -
Temperature dependence of the electrical characteristics up to 370 K of amorphous In-Ga-ZnO thin film transistors
(2016)© 2015 Elsevier Ltd.The temperature dependence in the typical temperature operating range from300 K up to 370 K of the electrical characteristics of IGZO TFTs fabricated at temperatures not exceeding 200 °C is presented ...