Centro Universitario FEI: Recent submissions
Now showing items 1501-1520 of 2258
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Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45 rotated substrates
(2013)This paper studies the impact of the 45 substrate rotation on the low-frequency noise (LFN) of triple gate nFinFETs. The overall LFN has been extracted for both standard and 45 substrate rotated devices of several fin ... -
Double-gate junctionless transistor model including short-channel effects
(2015)© 2015 IOP Publishing Ltd.This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), ... -
Junctionless multiple-gate transistors for analog applications
(2011)This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. ... -
A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors
(2013)This work proposes a physically-based definition for the threshold voltage, VTH, of junctionless nanowire transistors and a methodology to extract it. The VTH is defined as the point of equal magnitude for the drift and ... -
The zero temperature coefficient in junctionless nanowire transistors
(2012)This Letter presents an analysis of the zero temperature coefficient (ZTC) bias in junctionless nanowire transistors (JNTs). Unlike in previous works, which had shown that JNT did not present a ZTC point, this work shows ... -
3D simulation of triple-gate MOSFETs with different mobility regions
(2011-07-05)In this paper we present a new approach for analyzing 3D structure triple-gate MOSFETs using three different regions, one at the top and two in the sidewalls of the fin, which allows for considering different carrier ... -
An explicit multi-exponential model for semiconductor junctions with series and shunt resistances
(2011)An alternative explicit multi-exponential model is proposed to describe multiple, arbitrary ideality factor, conduction mechanisms in semiconductor junctions with parasitic series and shunt resistances. This Lambert function ... -
Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs
(2013)In this work a comparison between the performance of current mirrors implemented with uniformly doped and graded-channel (GC) transistors operating down to low temperature (150 K) is presented. This analysis has been carried ... -
Trap density characterization through low-frequency noise in junctionless transistors
(2013)This work evaluates, for the first time, the trap density of Junctionless Nanowire Transistors (JNTs) of two technologies produced with different gate dielectrics through the low-frequency noise (LFN) characterization. ... -
Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs
(2012)This work presents the analog performance of n-type triple-gate MuGFETs with high-k dielectrics and TiN gate material fabricated in 45° rotated SOI substrates comparing their performance with standard MuGFETs fabricated ... -
Cryogenic operation of junctionless nanowire transistors
(2011)This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and ... -
Threshold voltage in junctionless nanowire transistors
(2011)This work presents a physically based analytical model for the threshold voltage in junctionless nanowire transistors (JNTs). The model is based on the solution of the two-dimensional Poisson equation and includes the ... -
Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures
(2009)This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SOI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of ... -
Direct determination of threshold condition in DG-MOSFETs from the g m/ID curve
(2011)In this work we apply the current-based threshold voltage definition (equality between the drift and diffusion components of drain current) to intrinsic symmetric double-gate MOSFETs. We show that the half maximum point ...