Centro Universitario FEI: Recent submissions
Now showing items 1381-1400 of 2182
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Selection of suitable hand gestures for reliable myoelectric human computer interface
(2015)© Castro et al.Background: Myoelectric controlled prosthetic hand requires machine based identification of hand gestures using surface electromyogram (sEMG) recorded from the forearm muscles. This study has observed that ... -
sEMG feature evaluation for identification of elbow angle resolution in graded arm movement
(2014)© 2014 Castro et al.Automatic and accurate identification of elbow angle from surface electromyogram (sEMG) is essential for myoelectric controlled upper limb exoskeleton systems. This requires appropriate selection of ... -
An accurate closed-expression model for FinFETs parasitic resistance
(2015)© 2015 Elsevier Ltd. All rights reserved.A new closed-expression analytic model for parasitic resistance of FinFETs (Fin-Field-Effect-Transistors), which allows a fast estimation of this parasitic element, is proposed and ... -
An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models
(2017)© 2016 Elsevier LtdThe Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150 °C, for the first time to the best ... -
Electrical characterization of vertically stacked p-FET SOI nanowires
(2018)© 2017 Elsevier LtdThis work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional ... -
Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs
(2018)© 2018 Elsevier LtdThis work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate ... -
Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures
(2017)© 2017 IOP Publishing Ltd.This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and ... -
High temperature effects on harmonic distortion in submicron SOI graded-channel MOSFETs
(2011)The effect of elevated temperature on the harmonic distortion in Graded-Channel MOSFETs is presented in this work. The Graded-Channel devices show interesting advantages in terms of nonlinear behavior compared to classical ... -
Physical insights on the dynamic response of SOI n-and p-type junctionless nanowire transistors
(2018)© 2018, Brazilian Microelectronics Society. All rights reserved.— This work evaluates, for the first time, the roles of the intrinsic capacitances and the series resistance on the dynamic response of p-and n-type Junctionless ... -
Substrate bias influence on the operation of junctionless nanowire transistors
(2014)The aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental results, accomplished by modeled data. The threshold voltage, ... -
Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs
(2019)© 2019 Elsevier LtdThis work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow ... -
Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K
(2017)© 2017 Elsevier LtdThe linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed ... -
Junctionless nanowire transistors parameters extraction based on drain current measurements
(2019)© 2019 Elsevier LtdThe aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As ... -
Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range
(2019)© 2019 Elsevier LtdThis paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics ...