Centro Universitario FEI: Recent submissions
Now showing items 1361-1380 of 2258
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VI-Based Measurement System Focusing on Space Applications
(2017)© 2017, Springer Science+Business Media New York.This article describes in detail a custom, high-performance, compact, flexible and reconfigurable test equipment. This measurement system is able to perform, locally or ... -
Electrical behavior of the Diamond layout style for MOSFETs in X-rays ionizing radiation environments
(2015)© 2015 Elsevier B.V. All rights reserved.This paper aims to describe some innovative layout styles, which are capable to boost the electrical performance and, in the same time, the Total Ionizing Dose (TID) tolerance of ... -
An Innovative Ellipsoidal Layout Style to Further Boost the Electrical Performance of MOSFETs
(2015)© 1980-2012 IEEE.This letter describes the impact of using a new gate geometry (ellipsoidal) rather than the standard one (rectangular) to implement planar metal-oxide-semiconductor field-effect transistors (MOSFETs). Our ... -
Improving MOSFETs' TID Tolerance Through Diamond Layout Style
(2017)© 2001-2011 IEEE.This letter describes an experimental comparative study of the total ionizing dose (TID) effects due to Co-60 gamma irradiation between hexagonal (Diamond) and conventional rectangular gates metal-oxide ... -
FISH SOI MOSFET: Modeling, characterization and its application to improve the performance of analog ICs
(2011)This paper is conceptual and introduces a new transistor layout style called FISH SOI MOSFET (FSM). It is an evolution of the Diamond device (DSM) and specially designed to preserve the Longitudinal Corner Effect (LCE) to ... -
Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment
(2015)© 2015 IEEE.The impact of high-temperature effects is experimentally investigated in the octagonal layout style for planar silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs), named ... -
Compact diamond MOSFET model accounting for PAMDLE applicable down 150 nm node
(2014)© The Institution of Engineering and Technology 2014.The performance improvements for integrated circuit applications of silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) implemented ... -
Diamond MOSFET: An innovative layout to improve performance of ICs
(2010)A new planar MOSFET structure is proposed through a simple layout change, which modifies the gate geometric shape from rectangular to hexagonal in order to use the "corner effect concept" to enhance the resultant longitudinal ... -
Using diamond layout style to boost MOSFET frequency response of analogue IC
(2014)A way to improve the metal-oxide-semiconductor field effect transistor (MOSFET) analogue electrical performance, still little explored, is to modify their aspect form or ratio (AR) by the use of innovative layout styles. ... -
SOI Stacked Transistors Tolerance to Single-Event Effects
(2019)© 2001-2011 IEEE.This paper addresses a quantitative study of the reliability improvement of the stacked transistor structure. The susceptibility of integrated circuits to single-event effects caused by interaction with ... -
Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs
(2015)© 2014 Elsevier Ltd. All rights reserved.Three techniques to implement mechanical stress in n-channel Multiple Gate MOSFETs (MuGFETs) are investigated through 3D simulations and transconductance measurements. They are: ...