Toggle navigation
Repositório da Associação das Universidades Confiadas a Compañía de Jesús na América Latina
español
português (Brasil)
English
português (Brasil)
español
português (Brasil)
English
Entrar
Toggle navigation
Ver item
Página inicial
Centro Universitario FEI
Documentos - CUFEI
Ver item
Página inicial
Centro Universitario FEI
Documentos - CUFEI
Ver item
JavaScript is disabled for your browser. Some features of this site may not work without it.
Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K
Visualizar/
Abrir
Data
2017
Autor
Paz B.C.
Casse M.
Barraud S.
Reimbold G.
Vinet M.
Faynot O.
Pavanello M.A.
Metadata
Mostrar registro completo
URI
https://hdl.handle.net/20.500.12032/89526
Descrição
© 2016 Elsevier LtdThis work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires with fin width as narrow as 9.5 nm up to quasi-planar MOSFETs 10 μm-wide are analyzed. The fin width influence on the analog parameters is studied for n-type and p-MOSFETs with channel lengths of 10 μm and 40 nm, at room temperature. The temperature influence is analyzed on the analog performance down to 100 K for long channel n-MOSFETs by comparing the quasi-planar device to the nanowire with fin width of 14.5 nm. The intrinsic voltage gain, transconductance and output conductance are the most important figures of merit in this work. An explicit correlation between these figures of merit and the mobility behavior with temperature is demonstrated.
Collections
Documentos - CUFEI
Buscar DSpace
Esta coleção
Navegar
Todo o repositório
Comunidades e Coleções
Por data do documento
Autores
Títulos
Assuntos
Esta coleção
Por data do documento
Autores
Títulos
Assuntos
Minha conta
Entrar
Cadastro