Descripción
© 1980-2012 IEEE.This letter describes the impact of using a new gate geometry (ellipsoidal) rather than the standard one (rectangular) to implement planar metal-oxide-semiconductor field-effect transistors (MOSFETs). Our experimental results have been carried out using a 350-nm bulk complementary MOS technology node. We show that the proposed layout has been capable of increasing the ON-state and saturation drain currents in 2 and 3.2 times, respectively. In addition, the ellipsoidal MOSFET has been able to reduce the delay time constant by 61%. Therefore, we believe this new layout can be used as an alternative way to implement MOSFETs, boosting their analog electrical performance with an appropriate layout changing.
