| dc.contributor.author | Gimenez S.P. | |
| dc.contributor.author | Correia M.M. | |
| dc.contributor.author | Neto E.D. | |
| dc.contributor.author | Silva C.R. | |
| dc.date.accessioned | 2019-08-19T23:45:29Z | |
| dc.date.accessioned | 2023-05-03T20:36:27Z | |
| dc.date.available | 2019-08-19T23:45:29Z | |
| dc.date.available | 2023-05-03T20:36:27Z | |
| dc.date.issued | 2015 | |
| dc.identifier.citation | GIMENEZ, SALVADOR P.; CORREIA, MARCELLO M.; NETO, ENRICO D.; SILVA, CRISTINA R.. An Innovative Ellipsoidal Layout Style to Further Boost the Electrical Performance of MOSFETs. IEEE Electron Device Letters, v. 36, n. 7, p. 705-707, 2015. | |
| dc.identifier.issn | 0741-3106 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/89192 | |
| dc.description.abstract | © 1980-2012 IEEE.This letter describes the impact of using a new gate geometry (ellipsoidal) rather than the standard one (rectangular) to implement planar metal-oxide-semiconductor field-effect transistors (MOSFETs). Our experimental results have been carried out using a 350-nm bulk complementary MOS technology node. We show that the proposed layout has been capable of increasing the ON-state and saturation drain currents in 2 and 3.2 times, respectively. In addition, the ellipsoidal MOSFET has been able to reduce the delay time constant by 61%. Therefore, we believe this new layout can be used as an alternative way to implement MOSFETs, boosting their analog electrical performance with an appropriate layout changing. | |
| dc.relation.ispartof | IEEE Electron Device Letters | |
| dc.rights | Acesso Restrito | |
| dc.title | An Innovative Ellipsoidal Layout Style to Further Boost the Electrical Performance of MOSFETs | |
| dc.type | Artigo | |
