Analysis of the leakage current in junctionless nanowire transistors

Abstract

This letter presents an analysis of the leakage current in Junctionless Nanowire Transistors. The analysis is performed using experimental data together with three-dimensional numerical simulations. The influences of the temperature, device dimensions, and doping concentration have been studied. The results of inversion-mode devices of similar dimensions are also presented for comparison purpose. © 2013 AIP Publishing LLC.