Analysis of the leakage current in junctionless nanowire transistors
| dc.contributor.author | Trevisoli R. | |
| dc.contributor.author | Trevisoli Doria R. | |
| dc.contributor.author | De Souza M. | |
| dc.contributor.author | Antonio Pavanello M. | |
| dc.date.accessioned | 2019-08-19T23:45:12Z | |
| dc.date.available | 2019-08-19T23:45:12Z | |
| dc.date.issued | 2013 | |
| dc.identifier.citation | SOUZA, Michelly de; TREVISOLI, Renan D.; DORIA, Rodrigo Trevisoli; PAVANELLO, Marcelo A.;PAVANELLO, M. A.;PAVANELLO, M.;PAVANELLO, M.A.;PAVANELLO, MARCELO;ANTONIO PAVANELLO, MARCELO. Analysis of the leakage current in junctionless nanowire transistors. Applied Physics Letters, v. 103, n. 20, p. 202103, 2013. | |
| dc.identifier.issn | 0003-6951 | |
| dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/1122 | |
| dc.description.abstract | This letter presents an analysis of the leakage current in Junctionless Nanowire Transistors. The analysis is performed using experimental data together with three-dimensional numerical simulations. The influences of the temperature, device dimensions, and doping concentration have been studied. The results of inversion-mode devices of similar dimensions are also presented for comparison purpose. © 2013 AIP Publishing LLC. | |
| dc.relation.ispartof | Applied Physics Letters | |
| dc.rights | Acesso Restrito | |
| dc.title | Analysis of the leakage current in junctionless nanowire transistors | |
| dc.type | Artigo |
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