Envíos recientes

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Trevisoli R.; Doria R.T.; Barraud S.; Pavanello M.A. (2019)

© 2019 Elsevier B.V.The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain ...

Underestimantion of Measured Self-Heating in Nanowires By Using Gate Resistance Technique

MARINIELLO, GENARO; CASSÉ, MIKÄEL; REIMBOLD, GILLES; PAVANELLO, MARCELO (2016)

Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistor and its Dependence on the Temperature

DORIA, Rodrigo Trevisoli; TREVISOLI, Renan D.; SOUZA, Michelly de; PAVANELLO, Marcelo A.;PAVANELLO, M. A.;PAVANELLO, M.;PAVANELLO, M.A.;PAVANELLO, MARCELO;ANTONIO PAVANELLO, MARCELO (2012)

Charge-based compact analytical model for triple-gate junctionless nanowire transistors

Avila-Herrera F.; Paz B.C.; Cerdeira A.; Estrada M.; Pavanello M.A. (2016)

© 2016 Elsevier Ltd.A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin height effects, a new 3-D ...

Junctionless nanowire transistors operation at temperatures down to 4.2 K

Trevisoli R.; De Souza M.; Doria R.T.; Kilchtyska V.; Flandre D.; Pavanello M.A. (2016)

© 2016 IOP Publishing Ltd.The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the ...

Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

Pavanello M.A.; De Souza M.; Ribeiro T.A.; Martino J.A.; Flandre D. (2016)

© 2016 IOP Publishing Ltd.This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped ...

Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior

de Souza M.; Pavanello M.A.; Martino J.A.; Simoen E.; Claeys C. (2007)

This work presents the impact of low temperature operation on the characteristics of uniaxially strained fully-depleted SOI nMOSFETs. Devices with channel lengths down to 160 nm were explored in the range 100-380 K. The ...

Drain current model for short-channel triple gate junctionless nanowire transistors

Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Faynot O.; Avila-Herrera F.; Cerdeira A.; Pavanello M.A. (2016)

© 2016 Elsevier LtdThis work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration ...

Analysis of the leakage current in junctionless nanowire transistors

Trevisoli R.; Trevisoli Doria R.; De Souza M.; Antonio Pavanello M. (2013)

This letter presents an analysis of the leakage current in Junctionless Nanowire Transistors. The analysis is performed using experimental data together with three-dimensional numerical simulations. The influences of the ...

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Doria R.T.; Trevisoli R.; de Souza M.; Barraud S.; Vinet M.; Faynot O.; Pavanello M.A. (2017)

© 2017 Elsevier B.V.This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire transistors (JNTs) on the substrate bias. ...

An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices

Trevisoli R.D.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A. (2012)

Triple-gate devices are considered a promising solution for sub-20 nm era. Strain engineering has also been recognized as an alternative due to the increase in the carriers mobility it propitiates. The simulation of strained ...

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K

Paz B.C.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A. (2017)

© 2016 Elsevier LtdThis work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires ...

The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear Regime

DORIA, Rodrigo Trevisoli; TREVISOLI, Renan Doria; DE SOUZA, Michelly; CUETO, Magali Estrada; CERDEIRA, Antonio; Pavanello, Marcelo Antonio (2014)

Centro Universitario FEI: Envíos recientes

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Underestimantion of Measured Self-Heating in Nanowires By Using Gate Resistance Technique

Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistor and its Dependence on the Temperature

Charge-based compact analytical model for triple-gate junctionless nanowire transistors

Junctionless nanowire transistors operation at temperatures down to 4.2 K

Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior

Drain current model for short-channel triple gate junctionless nanowire transistors

Analysis of the leakage current in junctionless nanowire transistors

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K

The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear Regime

In-depth low frequency noise evaluation of substrate rotation and strain engineering in N-type triple gate SOI Finfets

Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors

Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors

Compact core model for Symmetric Double-Gate Junctionless Transistors

On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors

Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors

Centro Universitario FEI: Envíos recientes

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors ﻿

Underestimantion of Measured Self-Heating in Nanowires By Using Gate Resistance Technique ﻿

Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistor and its Dependence on the Temperature ﻿

Charge-based compact analytical model for triple-gate junctionless nanowire transistors ﻿

Junctionless nanowire transistors operation at temperatures down to 4.2 K ﻿

Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature ﻿

Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior ﻿

Drain current model for short-channel triple gate junctionless nanowire transistors ﻿

Analysis of the leakage current in junctionless nanowire transistors ﻿

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization ﻿

An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices ﻿

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K ﻿

The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear Regime ﻿

In-depth low frequency noise evaluation of substrate rotation and strain engineering in N-type triple gate SOI Finfets ﻿

Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors ﻿

Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors ﻿

Compact core model for Symmetric Double-Gate Junctionless Transistors ﻿

On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration ﻿

Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors ﻿

Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors ﻿

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Underestimantion of Measured Self-Heating in Nanowires By Using Gate Resistance Technique

Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistor and its Dependence on the Temperature

Charge-based compact analytical model for triple-gate junctionless nanowire transistors

Junctionless nanowire transistors operation at temperatures down to 4.2 K

Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior

Drain current model for short-channel triple gate junctionless nanowire transistors

Analysis of the leakage current in junctionless nanowire transistors

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K

The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear Regime

In-depth low frequency noise evaluation of substrate rotation and strain engineering in N-type triple gate SOI Finfets

Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors

Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors

Compact core model for Symmetric Double-Gate Junctionless Transistors

On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors

Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors