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Substrate bias influence on the operation of junctionless nanowire transistors
(2014)
The aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental results, accomplished by modeled data. The threshold voltage, ...
Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs
(2019)
© 2019 Elsevier LtdThis work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow ...
Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K
(2017)
© 2017 Elsevier LtdThe linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed ...
Drain current model for short-channel triple gate junctionless nanowire transistors
(2016)
© 2016 Elsevier LtdThis work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration ...
Junctionless nanowire transistors parameters extraction based on drain current measurements
(2019)
© 2019 Elsevier LtdThe aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As ...
Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs
(2012)
This work presents the analog performance of n-type triple-gate MuGFETs with high-k dielectrics and TiN gate material fabricated in 45° rotated SOI substrates comparing their performance with standard MuGFETs fabricated ...
Approximate analytical expression for the tersminal voltage in multi-exponential diode models
(2013)
We propose a simple approximate solution for the terminal voltage as an explicit function of the terminal current for diodes which need to be modeled by two or more ideal diodes in parallel. As a result, this solution is ...
Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range
(2019)
© 2019 Elsevier LtdThis paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics ...
Compact model for short-channel symmetric double-gate junctionless transistors
(2015)
© 2015 Elsevier Ltd.Abstract In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage ...
Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors
(2016)
© The Institution of Engineering and Technology 2016.In this paper, the performance of asymmetric self-cascode (A-SC) fully depleted silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors ...