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Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors

Cerdeira A.; Estrada M.; Iniguez B.; Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A. (2013)

A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 × 1018 and 1 × 10 19 cm-3, as well as ...

Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors

Doria R.T.; Trevisoli R.; De Souza M.; Pavanello M.A. (2014)

This work presents an evaluation of the Low-Frequency Noise (LFN) exhibited by short-channel Junctionless Nanowire Transistors (JNTs). Unlike in previous works in which only the noise of n-type transistors was evaluated, ...

Trap density characterization through low-frequency noise in junctionless transistors

Doria R.T.; Trevisoli R.D.; De Souza M.; Pavanello M.A. (2013)

This work evaluates, for the first time, the trap density of Junctionless Nanowire Transistors (JNTs) of two technologies produced with different gate dielectrics through the low-frequency noise (LFN) characterization. ...

Substrate bias influence on the operation of junctionless nanowire transistors

Trevisoli R.; Doria R.T.; De Souza M.; Pavanello M.A. (2014)

The aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental results, accomplished by modeled data. The threshold voltage, ...

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K

Paz B.C.; Doria R.T.; Casse M.; Barraud S.; Reimbold G.; Vinet M.; Faynot O.; Pavanello M.A. (2017)

© 2017 Elsevier LtdThe linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed ...

Junctionless nanowire transistors parameters extraction based on drain current measurements

Trevisoli R.; Doria R.T.; de Souza M.; Barraud S.; Pavanello M.A. (2019)

© 2019 Elsevier LtdThe aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As ...

Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range

Pavanello M.A.; Cerdeira A.; Doria R.T.; Ribeiro T.A.; Avila-Herrera F.; Estrada M. (2019)

© 2019 Elsevier LtdThis paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics ...

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

Doria R.T.; Cerdeira A.; Raskin J.-P.; Flandre D.; Pavanello M.A. (2008)

In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-around (GAA) devices operating in saturation region for analog applications. The study has been performed through device ...

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Trevisoli R.; Doria R.T.; Barraud S.; Pavanello M.A. (2019)

© 2019 Elsevier B.V.The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain ...

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Doria R.T.; Trevisoli R.; de Souza M.; Barraud S.; Vinet M.; Faynot O.; Pavanello M.A. (2017)

© 2017 Elsevier B.V.This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire transistors (JNTs) on the substrate bias. ...