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Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs
(2018)
© 2018 Elsevier LtdThis work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate ...
Charge-based compact analytical model for triple-gate junctionless nanowire transistors
(2016)
© 2016 Elsevier Ltd.A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin height effects, a new 3-D ...
Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs
(2013)
In this work a comparison between the performance of current mirrors implemented with uniformly doped and graded-channel (GC) transistors operating down to low temperature (150 K) is presented. This analysis has been carried ...
Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs
(2019)
© 2019 Elsevier LtdThis work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow ...
Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K
(2017)
© 2017 Elsevier LtdThe linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed ...
Drain current model for short-channel triple gate junctionless nanowire transistors
(2016)
© 2016 Elsevier LtdThis work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration ...
Compact model for short-channel symmetric double-gate junctionless transistors
(2015)
© 2015 Elsevier Ltd.Abstract In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage ...
Double-gate junctionless transistor model including short-channel effects
(2015)
© 2015 IOP Publishing Ltd.This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), ...
Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K
(2017)
© 2016 Elsevier LtdThis work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires ...