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Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors
(2016)
© 2015 IEEE.This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which ...
Junctionless nanowire transistors operation at temperatures down to 4.2 K
(2016)
© 2016 IOP Publishing Ltd.The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the ...
On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration
(2016)
© 2015 Elsevier Ltd. All rights reserved.This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two ...