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A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors

Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A. (2013)

This work proposes a physically-based definition for the threshold voltage, VTH, of junctionless nanowire transistors and a methodology to extract it. The VTH is defined as the point of equal magnitude for the drift and ...

Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures

de Souza M.; Flandre D.; Pavanello M.A. (2009)

This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SOI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of ...

Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs

Pavanello M.A.; Souza M.D.; Martino J.A.; Simoen E.; Claeys C. (2012)

This work presents the analog performance of n-type triple-gate MuGFETs with high-k dielectrics and TiN gate material fabricated in 45° rotated SOI substrates comparing their performance with standard MuGFETs fabricated ...

Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

Pavanello M.A.; De Souza M.; Ribeiro T.A.; Martino J.A.; Flandre D. (2016)

© 2016 IOP Publishing Ltd.This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped ...

Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors

Doria R.T.; Trevisoli R.; De Souza M.; Pavanello M.A. (2014)

This work presents an evaluation of the Low-Frequency Noise (LFN) exhibited by short-channel Junctionless Nanowire Transistors (JNTs). Unlike in previous works in which only the noise of n-type transistors was evaluated, ...

Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors

Trevisoli R.; Doria R.T.; De Souza M.; Barraud S.; Vinet M.; Pavanello M.A. (2016)

© 2015 IEEE.This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which ...

Evaluation of graded-channel SOI MOSFET operation at high temperatures

Galeti M.; Pavanello M.A.; Martino J.A. (2006)

This paper presents a comparative analysis between graded-channel (GC) and conventional fully depleted SOI MOSFETs devices operating at high temperatures (up to 300 °C). The electrical characteristics such as threshold ...

Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications

Pavanello M.A.; Der Agopian P.G.; Martino J.A.; Flandre D. (2006)

We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a ...

High temperature effects on harmonic distortion in submicron SOI graded-channel MOSFETs

Emam M.; Pavanello M.A.; Danneville F.; Vanhoenacker-Janvier D.; Raskin J.-P. (2011)

The effect of elevated temperature on the harmonic distortion in Graded-Channel MOSFETs is presented in this work. The Graded-Channel devices show interesting advantages in terms of nonlinear behavior compared to classical ...

Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer

de Souza M.; Flandre D.; Pavanello M.A. (2008)

In this work the performance of graded-channel (GC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with GC ...