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Analytical model for the dynamic behavior of triple-gate junctionless nanowire transistors

Trevisoli R.; Doria R.T.; De Souza M.; Barraud S.; Vinet M.; Pavanello M.A. (2016)

© 2015 IEEE.This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which ...

Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures

Doria R.T.; Flandre D.; Trevisoli R.; De Souza M.; Pavanello M.A. (2017)

© 2017 IOP Publishing Ltd.This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and ...

Junctionless multiple-gate transistors for analog applications

Doria R.T.; Pavanello M.A.; Trevisoli R.D.; De Souza M.; Lee C.-W.; Ferain I.; Akhavan N.D.; Yan R.; Razavi P.; Yu R.; Kranti A.; Colinge J.-P. (2011)

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. ...

A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors

Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A. (2013)

This work proposes a physically-based definition for the threshold voltage, VTH, of junctionless nanowire transistors and a methodology to extract it. The VTH is defined as the point of equal magnitude for the drift and ...

The zero temperature coefficient in junctionless nanowire transistors

Trevisoli R.D.; Trevisoli Doria R.; De Souza M.; Das S.; Ferain I.; Antonio Pavanello M. (2012)

This Letter presents an analysis of the zero temperature coefficient (ZTC) bias in junctionless nanowire transistors (JNTs). Unlike in previous works, which had shown that JNT did not present a ZTC point, this work shows ...

Threshold voltage in junctionless nanowire transistors

Trevisoli R.D.; Doria R.T.; De Souza M.; Pavanello M.A. (2011)

This work presents a physically based analytical model for the threshold voltage in junctionless nanowire transistors (JNTs). The model is based on the solution of the two-dimensional Poisson equation and includes the ...

Junctionless nanowire transistors operation at temperatures down to 4.2 K

Trevisoli R.; De Souza M.; Doria R.T.; Kilchtyska V.; Flandre D.; Pavanello M.A. (2016)

© 2016 IOP Publishing Ltd.The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the ...

Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors

Trevisoli R.; Doria R.T.; De Souza M.; Pavanello M.A. (2015)

© 2015 Elsevier B.V. All rights reserved.Abstract This work proposes a method for extracting the energetic distribution of the interface trap density at the gate dielectric in Junctionless silicon Nanowire Transistors. The ...

Compact core model for Symmetric Double-Gate Junctionless Transistors

Cerdeira A.; Avila F.; Iniguez B.; De Souza M.; Pavanello M.A.; Estrada M. (2014)

A new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including ...

On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

De Souza M.; Flandre D.; Doria R.T.; Trevisoli R.; Pavanello M.A. (2016)

© 2015 Elsevier Ltd. All rights reserved.This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two ...