Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range
| dc.contributor.author | Pavanello M.A. | |
| dc.contributor.author | Cerdeira A. | |
| dc.contributor.author | Doria R.T. | |
| dc.contributor.author | Ribeiro T.A. | |
| dc.contributor.author | Avila-Herrera F. | |
| dc.contributor.author | Estrada M. | |
| dc.date.accessioned | 2019-08-19T23:45:13Z | |
| dc.date.accessioned | 2023-05-03T20:34:37Z | |
| dc.date.available | 2019-08-19T23:45:13Z | |
| dc.date.available | 2023-05-03T20:34:37Z | |
| dc.date.issued | 2019 | |
| dc.identifier.citation | Pavanello, Marcelo A.; CERDEIRA, Antonio; Doria, Rodrigo Trevisoli; RIBEIRO, Thales Augusto; HERRERA, FERNANDO AVILA; ESTRADA, MAGALI. Compact Modeling of Triple Gate Junctionless Mosfets for Accurate Circuit Design in a Wide Temperature Range. SOLID-STATE ELECTRONICS, v. 159, p. 116-122, 2019. | |
| dc.identifier.issn | 0038-1101 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/88848 | |
| dc.description.abstract | © 2019 Elsevier LtdThis paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room temperature up to 500 K. The model validation is performed by comparison against tridimensional numerical simulation and experimental data showing very good agreement, with continuous description of drain current and its derivatives in all regions of operation and temperatures. | |
| dc.relation.ispartof | Solid-State Electronics | |
| dc.rights | Acesso Restrito | |
| dc.title | Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range | |
| dc.type | Artigo |
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