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dc.contributor.authorTrevisoli R.
dc.contributor.authorDoria R.T.
dc.contributor.authorBarraud S.
dc.contributor.authorPavanello M.A.
dc.date.accessioned2019-08-19T23:45:13Z
dc.date.accessioned2023-05-03T20:33:05Z
dc.date.available2019-08-19T23:45:13Z
dc.date.available2023-05-03T20:33:05Z
dc.date.issued2019
dc.identifier.citationTREVISOLI, RENAN; Doria, Rodrigo Trevisoli; BARRAUD, SYLVAIN; Pavanello, Marcelo Antonio. Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors. MICROELECTRONIC ENGINEERING, v. 215, p. 111005, 2019.
dc.identifier.issn0167-9317
dc.identifier.urihttps://hdl.handle.net/20.500.12032/88552
dc.description.abstract© 2019 Elsevier B.V.The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain current model, which includes short channel effects influence. The surface potential and the occupied trap density equations are solved self consistently to obtain the traps influence in the static drain current, which is used to determine the trap-related noise. In this work, the low frequency noise of traps in discrete levels is analyzed. The model has been validated with 3D simulations considering different devices characteristics, biases and trap levels. Experimental results have also been used to demonstrate the model suitability.
dc.relation.ispartofMicroelectronic Engineering
dc.rightsAcesso Restrito
dc.titleModeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors
dc.typeArtigo


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