Test Modules Design for a SerDes Chip in 130 nm CMOS technology
Descripción
In this thesis, a DFT architecture is proposed for testing a high-speed SerDes circuit. This architecture suggests the implementation of three testing modules: a comparator, a linear-feedback shift register (LFSR) and a signal driver. By embedding these test modules to the SerDes, the circuit will be able to perform eight different operating modes for testing in addition to the functional mode. With these operating modes, the functionality of all the modules individually and collectively can be tested by the use of multiplexers and BIST.Consejo Nacional de Ciencia y Tecnología