Envíos recientes

Diseño de filtro rechaza banda y cálculo de Antipad para un PCB de alta velocidad

DeLaTorre-Aguirre, Jaime (ITESO, 2019-08)

Reporte de formación complementaria en área de concentración de sistemas digitales

Delgadillo-Casas, Francisco J. (ITESO, 2019-06)

A Linear Inverse Space Mapping Algorithm for Microwave Design in the Frequency and Transient Domains (poster)

Rayas-Sánchez, José E.; Lara-Rojo, Fernando; Martínez-Guerrero, Esteban (IEEE, 2004-06)

EM Parametric Study of Length Matching Elements Exploiting an ANSYS HFSS Matlab-Python Driver

Sánchez-Mesa, Rosa J.; Cortés-Hernández, Diego M.; Rayas-Sánchez, José E.; Brito-Brito, Zabdiel; DeLaMora-Hernández, Lizbeth (IEEE, 2018-12)

Selecting Surrogate-Based Modeling Techniques for Power Integrity Analysis

Leal-Romo, Felipe J.; Chávez-Hurtado, José L.; Rayas-Sánchez, José E. (IEEE, 2018-12)

A Novel High-Performance Length Matching Element for High-Speed Interconnect Differential Channels

Sánchez-Mesa, Rosa J.; Cortés-Hernández, Diego M.; Gálvez-Sahagún, Benjamín; Rayas-Sánchez, José E.; Brito-Brito, Zabdiel (IEEE, 2018-12)

A Digital Predistortion Technique Based on a NARX Network to Linearize GaN Class F Power Amplifiers (poster)

Aguilar-Lobo, Lina M.; García-Osorio, Alberto; Loo-Yau, José R.; Ortega-Cisneros, Susana; Moreno, Pablo; Rayas-Sánchez, José E.; Reynoso-Hernández, Apolinar (IEEE, 2014-08)

Optimizing Phase Settings of High-Frequency Voltage Regulators for Power Delivery Applications

Leal-Romo, Felipe J.; Silva-Perales, José L.; López-Limón, Carlos; Rayas-Sánchez, José E. (IEEE, 2018-05)

Jitter Tolerance Acceleration Using the Golden Section Optimization Technique

Viveros-Wacher, Andrés; Baca-Baylón, Ricardo; Rangel-Patiño, Francisco E.; Dávalos-Santana, Miguel A.; Vega-Ochoa, Édgar A.; Rayas-Sánchez, José E. (IEEE, 2018-02)

Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation

Rangel-Patiño, Francisco E.; Rayas-Sánchez, José E.; Hakim, Nagib (IEEE, 2018-10)

Design Optimization of a Planar Spiral Inductor Using Space Mapping

Leal-Romo, Felipe J.; Cabrera-Gómez, Marisol; Rayas-Sánchez, José E.; García-Mora, Daniel M. (IEEE, 2017-10)

A Historical Account and Technical Reassessment of the Broyden-based Input Space Mapping Optimization Algorithm

Rayas-Sánchez, José E. (IEEE, 2017-06)

Analog Fault Identification in RF Circuits using Artificial Neural Networks and Constrained Parameter Extraction

Viveros-Wacher, Andrés; Rayas-Sánchez, José E. (IEEE, 2018-08)

Analysis of the Implications of Stacked Devices in Nano-Scale Technologies for Analog Applications

Lomelí-Illescas, Ismael; Solís-Bustos, Sergio A.; Rayas-Sánchez, José E. (IEEE, 2017-03)

Design and Validation of a Portable Radio-Frequency Diathermy Prototype

Corres-Matamoros, Antonio; Martínez-Guerrero, Esteban; Rayas-Sánchez, José E. (IEEE, 2017-06)

Design of Experiments Implementation towards Optimization of Power Distribution Networks

Leal-Romo, Felipe J.; Rayas-Sánchez, José E.; He, Jiangqi (IEEE, 2017-02)

A Holistic Methodology for System Margining and Jitter Tolerance Optimization in Post-Silicon Validation

Rangel-Patiño, Francisco E.; Viveros-Wacher, Andrés; Rayas-Sánchez, José E.; Vega-Ochoa, Édgar A.; Duron-Rosales, Ismael; Hakim, Nagib (IEEE, 2016-12)

Universidad para la justicia

Narro-Monroy, Jorge A. (ITESO, 2017-08-22)

Direct Optimization of a PCI Express Link Equalization in Industrial Post-Silicon Validation

Rangel-Patiño, Francisco E.; Rayas-Sánchez, José E.; Vega-Ochoa, Édgar A.; Hakim, Nagib (IEEE, 2018-03)

High-Speed Links Receiver Optimization in Post-Silicon Validation Exploiting Broyden-based Input Space Mapping

Rangel-Patiño, Francisco E.; Rayas-Sánchez, José E.; Viveros-Wacher, Andrés; Vega-Ochoa, Édgar A.; Hakim, Nagib (IEEE, 2018-08)

Instituto Tecnológico y de Estudios Superiores de Occidente - ITESO: Envíos recientes

Diseño de filtro rechaza banda y cálculo de Antipad para un PCB de alta velocidad ﻿

Reporte de formación complementaria en área de concentración de sistemas digitales ﻿

A Linear Inverse Space Mapping Algorithm for Microwave Design in the Frequency and Transient Domains (poster) ﻿

EM Parametric Study of Length Matching Elements Exploiting an ANSYS HFSS Matlab-Python Driver ﻿

Selecting Surrogate-Based Modeling Techniques for Power Integrity Analysis ﻿

A Novel High-Performance Length Matching Element for High-Speed Interconnect Differential Channels ﻿

A Digital Predistortion Technique Based on a NARX Network to Linearize GaN Class F Power Amplifiers (poster) ﻿

Optimizing Phase Settings of High-Frequency Voltage Regulators for Power Delivery Applications ﻿

Jitter Tolerance Acceleration Using the Golden Section Optimization Technique ﻿

Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation ﻿

Design Optimization of a Planar Spiral Inductor Using Space Mapping ﻿

A Historical Account and Technical Reassessment of the Broyden-based Input Space Mapping Optimization Algorithm ﻿

Analog Fault Identification in RF Circuits using Artificial Neural Networks and Constrained Parameter Extraction ﻿

Analysis of the Implications of Stacked Devices in Nano-Scale Technologies for Analog Applications ﻿

Design and Validation of a Portable Radio-Frequency Diathermy Prototype ﻿

Design of Experiments Implementation towards Optimization of Power Distribution Networks ﻿

A Holistic Methodology for System Margining and Jitter Tolerance Optimization in Post-Silicon Validation ﻿

Universidad para la justicia ﻿

Direct Optimization of a PCI Express Link Equalization in Industrial Post-Silicon Validation ﻿

High-Speed Links Receiver Optimization in Post-Silicon Validation Exploiting Broyden-based Input Space Mapping ﻿