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Post-silicon Receiver Equalization Metamodeling by Artificial Neural Networks

Rangel-Patiño, Francisco E.; Rayas-Sánchez, José E.; Viveros-Wacher, Andrés; Chávez-Hurtado, José L.; Vega-Ochoa, Edgar A.; Hakim, Nagib (IEEE, 2019-04)

Industry-Oriented Research Projects on Computer-Aided Design of High-Frequency Circuits and Systems at ITESO Mexico

Rayas-Sánchez, José E.; Rangel-Patiño, Francisco E.; Viveros-Wacher, Andrés; Chávez-Hurtado, José L.; Del-Rey, Juan R.; Leal-Romo, Felipe J.; Brito-Brito, Zabdiel (EuMA, 2018-09)

Analog Fault Identification in RF Circuits using Artificial Neural Networks and Constrained Parameter Extraction

Viveros-Wacher, Andrés; Rayas-Sánchez, José E. (IEEE, 2018-08)

System Margining Surrogate-Based Optimization in Post-Silicon Validation

Rangel-Patiño, Francisco E.; Chávez-Hurtado, José L.; Viveros-Wacher, Andrés; Rayas-Sánchez, José E. (IEEE, 2017-09)

Fast jitter tolerance testing for high-speed serial links in post-silicon validation

Viveros-Wacher, Andrés; Baca-Baylón, Ricardo; Silva-Cortés, Johana L.; Vega-Ochoa, Edgar A.; Rayas-Sánchez, José E.; Rangel-Patiño, Francisco E. (IEEE, 2021-11)

Analog Gross Fault Identification in RF Circuits using Neural Models and Constrained Parameter Extraction

Viveros-Wacher, Andrés; Rayas-Sánchez, José E.; Brito-Brito, Zabdiel (IEEE, 2019-06)

A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation

Rangel-Patiño, Francisco E.; Viveros-Wacher, Andrés; Rayas-Sánchez, José E.; Duron-Rosales, Ismael; Vega-Ochoa, Édgar A.; Hakim, Nagib; López-Miralrio, Enrique (IEEE, 2020-06)

Eye Diagram Optimization based on Design of Experiments (DoE) to Accelerate Industrial Testing of High Speed Links

Viveros-Wacher, Andrés; Rayas-Sánchez, José E. (IEEE, 2016-12)

Eye Diagram System Margining Surrogate-Based Optimization in a Server Silicon Validation Platform

Rangel-Patiño, Francisco E.; Chávez-Hurtado, José L.; Viveros-Wacher, Andrés; Rayas-Sánchez, José E.; Hakim, Nagib (EuMA, 2017-10)

Jitter Tolerance Acceleration Using the Golden Section Optimization Technique

Viveros-Wacher, Andrés; Baca-Baylón, Ricardo; Rangel-Patiño, Francisco E.; Dávalos-Santana, Miguel A.; Vega-Ochoa, Edgar A.; Rayas-Sánchez, José E. (IEEE, 2018-02)