A Holistic Methodology for System Margining and Jitter Tolerance Optimization in Post-Silicon Validation

Rangel-Patiño, Francisco E.; Viveros-Wacher, Andrés; Rayas-Sánchez, José E.; Vega-Ochoa, Edgar A.; Duron-Rosales, Ismael; Hakim, Nagib

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Date

2016-12

Author

Rangel-Patiño, Francisco E.

Viveros-Wacher, Andrés

Rayas-Sánchez, José E.

Vega-Ochoa, Edgar A.

Duron-Rosales, Ismael

Hakim, Nagib

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URI

https://hdl.handle.net/20.500.12032/69127

Description

The optimization of receiver analog circuitry in modern high-speed input/output (HSIO) links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose an innovative objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-Si validation time.

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