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dc.rights.licenseLicencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC BY-NC-ND 4.0)
dc.contributor.authorMolina Robles, Roberto
dc.contributor.authorSolera Bolanos, Edgar
dc.contributor.authorGarcía Ramírez, Ronny
dc.contributor.authorChacón Rodríguez, Alfonso
dc.contributor.authorRimolo Donadio, Renato
dc.contributor.authorArnaud Maceira, Alfredo
dc.date.accessioned2021-10-21T18:07:06Z
dc.date.accessioned2022-09-21T22:19:39Z
dc.date.available2021-10-21T18:07:06Z
dc.date.available2022-09-21T22:19:39Z
dc.date.issued2020
dc.identifier.urihttps://hdl.handle.net/20.500.12032/46674
dc.description.abstractThe structure of a functional verification flow used for the design of a RISC-V core is presented. The paper offers a guide on the test-planning used and details of the flow architecture, showing how to integrate the Universal Verification Methodology with the required, reference models, while implementing key futures in standard verification environments, such as testing regressions and code and structural coverage. The designed flow is compact yet efficient, making it affordable for small design teams, without requiring extra investment other than the already necessary licenses for RTL synthesis and the eventual fabrication of the chip.es
dc.description.sponsorshipAgencia Nacional de Investigación e Innovación
dc.format.mimetypeapplication/pdf
dc.language.isoenes
dc.publisherIEEEes
dc.relation.ispartof3rd Conference on PhD Research in Microelectronics and Electronics, 2020
dc.subjectFunctional verificationes
dc.subjectRISC-V 321es
dc.subjectUVMes
dc.subjectSystem Veriloges
dc.subjectEDA toolses
dc.subjectArchitecturees
dc.subjectTest generationes
dc.subjectCompileres
dc.subjectProcessores
dc.subjectSimulationes
dc.subjectCoveragees
dc.subjectRegressiones
dc.subjectReference modeles
dc.titleA compact functional verification flow for a RISC-V 321 based corees
dc.typeArtículoes


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