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dc.contributor.authorDoria R.T.
dc.contributor.authorFlandre D.
dc.contributor.authorTrevisoli R.
dc.contributor.authorDe Souza M.
dc.contributor.authorPavanello M.A.
dc.identifier.citationDORIA, R.T.; FLANDRE, D.; TREVISOLI, R D; DE SOUZA, Michelly; PAVANELLO, M. A.. Effect of the Back Bias on the Analog Performance of Standard FD and UTBB Transistors-Based Self-Cascode Structures. Semiconductor Science and Technology, v. 32, p. 1-10, 2017.
dc.description.abstract© 2017 IOP Publishing Ltd.This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and UTBB fully depleted (FD) SOI MOSFETs to the structures and has shown that a voltage gain improvement of about 7 dB is obtained when a forward back bias is applied to the drain-sided transistor of standard FD devices-based structure. In the case of UTBB transistors, an improvement larger than 5 dB of the output voltage gain is shown depending on the back bias applied to both n- or p-type devices. Finally, it is shown that the mirroring precision of current mirrors composed by SC structures can be more than 20% better than the one composed by single devices and the improvement is better when adequate back bias is applied.
dc.relation.ispartofSemiconductor Science and Technology
dc.rightsAcesso Restrito
dc.titleEffect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures

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