| dc.contributor.author | Perin A.L. | |
| dc.contributor.author | Pereira A.S.N. | |
| dc.contributor.author | Buhler R.T. | |
| dc.contributor.author | Da Silveira M.A.G. | |
| dc.contributor.author | Giacomini R.C. | |
| dc.date.accessioned | 2019-08-19T23:45:27Z | |
| dc.date.available | 2019-08-19T23:45:27Z | |
| dc.date.issued | 2019 | |
| dc.identifier.citation | PERIN, ANDRE L.; PEREIRA, ARIANNE S. N.; BUHLER, RUDOLF T.; DA SILVEIRA, MARCILEI A. G.; GIACOMINI, RENATO C.. SOI Stacked Transistors Tolerance to Single-Event Effects. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, v. 19, p. 393-401, 2019. | |
| dc.identifier.issn | 1558-2574 | |
| dc.identifier.uri | https://repositorio.fei.edu.br/handle/FEI/1297 | |
| dc.description.abstract | © 2001-2011 IEEE.This paper addresses a quantitative study of the reliability improvement of the stacked transistor structure. The susceptibility of integrated circuits to single-event effects caused by interaction with ionizing particles is analyzed at the semiconductor level, as well as at the device and circuit levels considering the replacement of each transistor by a stacked silicon-on-insulator (SOI) array. Up-To-date technologic nodes were used as inputs for the simulation and reliability models. A stochastic Markov model was proposed and evaluated. The model output pointed the stacked array as a real alternative for high-reliability in future applications, with exceptional results. For a 10^{5} device-count integrated circuit, a success probability of 80% is reached for missions over 100 000 h in the commercial flights altitude, while for the single transistor system, this value is reached for missions under 100 h. | |
| dc.relation.ispartof | IEEE Transactions on Device and Materials Reliability | |
| dc.rights | Acesso Restrito | |
| dc.title | SOI Stacked Transistors Tolerance to Single-Event Effects | |
| dc.type | Artigo | |
