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dc.contributor.authorGaleti M.
dc.contributor.authorPavanello M.A.
dc.contributor.authorMartino J.A.
dc.date.accessioned2019-08-19T23:45:08Z
dc.date.available2019-08-19T23:45:08Z
dc.date.issued2006
dc.identifier.citationGALETI, Milene; PAVANELLO, Marcelo A.; MARTINO, João Antonio. Evaluation of graded-channel SOI MOSFET operation at high temperatures. Microelectronics Journal, v. 37, n. 7, p. 601-607, 2006.
dc.identifier.issn0026-2692
dc.identifier.urihttps://repositorio.fei.edu.br/handle/FEI/1066
dc.description.abstractThis paper presents a comparative analysis between graded-channel (GC) and conventional fully depleted SOI MOSFETs devices operating at high temperatures (up to 300 °C). The electrical characteristics such as threshold voltage and subthreshold slope were obtained experimentally and by two-dimensional numerical simulations. The results indicated that GC transistors present nearly the same behavior as the conventional SOI MOSFET devices with similar channel length. Experimental analysis of the gm/IDS ratio and Early voltage demonstrated that in GC devices the low-frequency open-loop gain is significantly improved in comparison to conventional SOI devices at room and at high-temperature due to the Early voltage increase. The multiplication factor and parasitic bipolar transistor gain obtained by two-dimensional numerical simulations allowed the analysis of the breakdown voltage, which was demonstrated to be improved in the GC as compared to conventional SOI transistors in thin silicon layer devices in the whole temperature range under analysis. © 2005 Elsevier Ltd. All rights reserved.
dc.relation.ispartofMicroelectronics Journal
dc.rightsAcesso Restrito
dc.titleEvaluation of graded-channel SOI MOSFET operation at high temperatures
dc.typeArtigo


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