Centro Universitario FEI: Recent submissions
Itens para a visualização no momento 1521-1540 of 2258
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Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer
(2008)In this work the performance of graded-channel (GC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with GC ... -
Cryogenic operation of FinFETs aiming at analog applications
(2009)FinFETs are recognized as promising candidates for the CMOS nanometer era. In this paper the most recent results for cryogenic operation of FinFETs will be demonstrated with special emphasis on analog applications. Threshold ... -
Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation
(2008)In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-around (GAA) devices operating in saturation region for analog applications. The study has been performed through device ... -
Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs
(2008)This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is ... -
Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape
(2009)The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that ... -
Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS
(2011)This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this ... -
Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications
(2006)We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a ... -
Analysis of temperature-induced saturation threshold voltage degradation in deep-submicrometer ultrathin SOI MOSFETs
(2005)This paper presents a systematic study of the temperature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed ... -
Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor
(2005)In this paper, we analyze the previously unexpected advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters. The ... -
Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs
(2007)This work studies the impact of uniaxial, biaxial and combined uniaxial-biaxial strain on the linearity of nMOSFETs from a 65 nm fully depleted (FD) SOI technology. The total harmonic distortion (THD) and third-order ... -
The low-frequency noise behaviour of graded-channel SOI nMOSFETs
(2007)It is shown that the low-frequency noise in graded-channel (GC) SOI nMOSFETs is generally of the flicker or 1/f noise type. The corresponding input-referred noise spectral density is markedly higher than for the conventional ... -
Impact of halo implantation on 0.13 μm floating body partially depleted SOI n-MOSFETs in low temperature operation
(2005)This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation. Parameters such as the drain ... -
High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures
(2005)This work studies the use of channel engineering by means of graded-channel profile on double gate SOI MOSFETs for improving the analog performance and comparing their output characteristics with conventional double gate ... -
Evaluation of triple-gate FinFETs with SiO2-HfO2-TiN gate stack under analog operation
(2007)This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation ... -
A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation
(2005)In this work a continuous analytical model for analog simulation of submicron asymmetrically doped silicon-on-insulator (SOI) nMOSFET using the graded-channel (GC) architecture, valid from weak to strong inversion regimes, ... -
Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS
(2006)This paper studies the performance of operational transconductance amplifiers (OTAs) fabricated with Graded-Channel (GC) SOI nMOSFETs and designed to provide high open-loop voltage gain or high gain-bandwidth characteristics. ...