Now showing items 1-6 of 6
Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures
© 2017 IOP Publishing Ltd.This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and ...
Junctionless nanowire transistors operation at temperatures down to 4.2 K
© 2016 IOP Publishing Ltd.The aim of this work is to analyze the operation of junctionless nanowire transistors down to the liquid helium temperature. The drain current, the transconductance, the output conductance, the ...
On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration
© 2015 Elsevier Ltd. All rights reserved.This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two ...
Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs
In this work a comparison between the performance of current mirrors implemented with uniformly doped and graded-channel (GC) transistors operating down to low temperature (150 K) is presented. This analysis has been carried ...
Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature
© 2016 IOP Publishing Ltd.This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped ...
A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation
In this work a continuous analytical model for analog simulation of submicron asymmetrically doped silicon-on-insulator (SOI) nMOSFET using the graded-channel (GC) architecture, valid from weak to strong inversion regimes, ...