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Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors
(2015)
© 2015 Elsevier B.V. All rights reserved.Abstract This work proposes a method for extracting the energetic distribution of the interface trap density at the gate dielectric in Junctionless silicon Nanowire Transistors. The ...
Compact core model for Symmetric Double-Gate Junctionless Transistors
(2014)
A new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including ...
Direct determination of threshold condition in DG-MOSFETs from the g m/ID curve
(2011)
In this work we apply the current-based threshold voltage definition (equality between the drift and diffusion components of drain current) to intrinsic symmetric double-gate MOSFETs. We show that the half maximum point ...
On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration
(2016)
© 2015 Elsevier Ltd. All rights reserved.This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two ...
An explicit multi-exponential model for semiconductor junctions with series and shunt resistances
(2011)
An alternative explicit multi-exponential model is proposed to describe multiple, arbitrary ideality factor, conduction mechanisms in semiconductor junctions with parasitic series and shunt resistances. This Lambert function ...
Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors
(2013)
A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 × 1018 and 1 × 10 19 cm-3, as well as ...
Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs
(2013)
In this work a comparison between the performance of current mirrors implemented with uniformly doped and graded-channel (GC) transistors operating down to low temperature (150 K) is presented. This analysis has been carried ...
Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature
(2016)
© 2016 IOP Publishing Ltd.This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped ...
Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors
(2014)
This work presents an evaluation of the Low-Frequency Noise (LFN) exhibited by short-channel Junctionless Nanowire Transistors (JNTs). Unlike in previous works in which only the noise of n-type transistors was evaluated, ...
Trap density characterization through low-frequency noise in junctionless transistors
(2013)
This work evaluates, for the first time, the trap density of Junctionless Nanowire Transistors (JNTs) of two technologies produced with different gate dielectrics through the low-frequency noise (LFN) characterization. ...