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Now showing items 11-18 of 18
Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation
(2008)
In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-around (GAA) devices operating in saturation region for analog applications. The study has been performed through device ...
Impact of halo implantation on 0.13 μm floating body partially depleted SOI n-MOSFETs in low temperature operation
(2005)
This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation. Parameters such as the drain ...
Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs
(2008)
This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is ...
High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures
(2005)
This work studies the use of channel engineering by means of graded-channel profile on double gate SOI MOSFETs for improving the analog performance and comparing their output characteristics with conventional double gate ...
Evaluation of triple-gate FinFETs with SiO2-HfO2-TiN gate stack under analog operation
(2007)
This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation ...
Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape
(2009)
The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that ...
A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation
(2005)
In this work a continuous analytical model for analog simulation of submicron asymmetrically doped silicon-on-insulator (SOI) nMOSFET using the graded-channel (GC) architecture, valid from weak to strong inversion regimes, ...
Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS
(2006)
This paper studies the performance of operational transconductance amplifiers (OTAs) fabricated with Graded-Channel (GC) SOI nMOSFETs and designed to provide high open-loop voltage gain or high gain-bandwidth characteristics. ...