Now showing items 1-3 of 3
Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures
© 2017 IOP Publishing Ltd.This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and ...
Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K
© 2017 Elsevier LtdThe linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed ...
Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization
© 2017 Elsevier B.V.This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire transistors (JNTs) on the substrate bias. ...