dc.contributor.author | Benfica J. | |
dc.contributor.author | Green B. | |
dc.contributor.author | Porcher B.C. | |
dc.contributor.author | Poehls L.B. | |
dc.contributor.author | Vargas F. | |
dc.contributor.author | Medina N.H. | |
dc.contributor.author | Added N. | |
dc.contributor.author | De Aguiar V.A.P. | |
dc.contributor.author | Macchione E.L.A. | |
dc.contributor.author | Aguirre F. | |
dc.contributor.author | Silveira M.A.G. | |
dc.contributor.author | Perez M. | |
dc.contributor.author | Sofo Haro M. | |
dc.contributor.author | Sidelnik I. | |
dc.contributor.author | Blostein J. | |
dc.contributor.author | Lipovetzky J. | |
dc.contributor.author | Bezerra E.A. | |
dc.date.accessioned | 2019-08-19T23:47:19Z | |
dc.date.accessioned | 2023-05-03T20:39:03Z | |
dc.date.available | 2019-08-19T23:47:19Z | |
dc.date.available | 2023-05-03T20:39:03Z | |
dc.date.issued | 2016 | |
dc.identifier.citation | VARGAS, FABIAN; BENFICA, J.; POEHLS, L. B.; HARO, M. S.; SILVEIRA, M. A. G.; MEDINA, N. H.; ADDED, N.; V. A. P. Aguiar; BEZERRA, E. A.; LIPOVETZKY, J.; BLOSTEIN, J.; SIDELNIK, I.. Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects. IEEE Transactions on Nuclear Science, v. 63, p. 1294-1300, 2016. | |
dc.identifier.issn | 0018-9499 | |
dc.identifier.uri | https://hdl.handle.net/20.500.12032/89696 | |
dc.description.abstract | © 2016 IEEE.This work proposes a novel methodology to evaluate SRAM-based FPGA's susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, Total-Ionizing Dose (TID) and TID-imprinted effect on BlockRAM cells. The proposed procedure is demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletron accelerator for the SEU test with heavy-ions, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. In order to observe the TID-induced imprint effect inside the BlockRAM cells, a second SEU test with neutrons was performed with Americium/Beryllium (241 AmBe). The noise was injected into the power supply bus according to the IEC 61.000-4-29 standard and consisted of voltage dips with 16.67% and 25% of the FPGA's VDD at frequencies of 10 Hz and 5 kHz, respectively. At the end of the experiment, the combined SEU failure rate, given in error/bit.day, is calculated for the FPGA's BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID. | |
dc.relation.ispartof | IEEE Transactions on Nuclear Science | |
dc.rights | Acesso Restrito | |
dc.title | Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects | |
dc.type | Artigo | |