Surface Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors
dc.contributor.author | TREVISOLI, R D | |
dc.contributor.author | DORIA, R. T. | |
dc.contributor.author | DE SOUZA, Michelly | |
dc.contributor.author | DAS, Samaresh | |
dc.contributor.author | FERAIN, I. | |
dc.contributor.author | PAVANELLO, Marcelo A. | |
dc.date.accessioned | 2019-08-19T23:45:10Z | |
dc.date.accessioned | 2023-05-03T20:37:38Z | |
dc.date.available | 2019-08-19T23:45:10Z | |
dc.date.available | 2023-05-03T20:37:38Z | |
dc.date.issued | 2012 | |
dc.identifier.citation | TREVISOLI, R D; DORIA, R. T.; DE SOUZA, Michelly; DAS, Samaresh; FERAIN, I.; PAVANELLO, Marcelo A.. Surface Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors. IEEE Transactions on Electron Devices, v. 59, n. 12, p. 3510-3518, 2012. | |
dc.identifier.issn | 0018-9383 | |
dc.identifier.uri | https://hdl.handle.net/20.500.12032/89427 | |
dc.relation.ispartof | IEEE Transactions on Electron Devices | |
dc.rights | Acesso Aberto | |
dc.title | Surface Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors | pt_BR |
dc.type | Artigo | pt_BR |
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