| dc.contributor.author | Gimenez S.P. | |
| dc.contributor.author | Pavanello M.A. | |
| dc.contributor.author | Martino J.A. | |
| dc.contributor.author | Flandre D. | |
| dc.date.accessioned | 2019-08-19T23:45:08Z | |
| dc.date.accessioned | 2023-05-03T20:36:23Z | |
| dc.date.available | 2019-08-19T23:45:08Z | |
| dc.date.available | 2023-05-03T20:36:23Z | |
| dc.date.issued | 2006 | |
| dc.identifier.citation | GIMENEZ, Salvador Pinillos; PAVANELLO, Marcelo A.; MARTINO, João Antonio; FLANDRE, Denis. Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS. Microelectronics Journal, v. 37, n. 1, p. 31-37, 2006. | |
| dc.identifier.issn | 0026-2692 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12032/89182 | |
| dc.description.abstract | This paper studies the performance of operational transconductance amplifiers (OTAs) fabricated with Graded-Channel (GC) SOI nMOSFETs and designed to provide high open-loop voltage gain or high gain-bandwidth characteristics. Different design targets were taken in account such as similar power dissipation, transconductance over drain current ratio and die area. Comparisons with OTAs made with conventional SOI nMOSFETs, are performed showing that the GC OTAs presents larger open-loop voltage gain without degrading the phase margin, unit gain frequency and slew rate simultaneously with a significant required die area reduction depending on LLD/L ratio used. Circuit simulations and experimental results are used to qualify the analysis. © 2005 Elsevier Ltd. All rights reserved. | |
| dc.relation.ispartof | Microelectronics Journal | |
| dc.rights | Acesso Restrito | |
| dc.title | Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS | |
| dc.type | Artigo | |
